Ic card

ABSTRACT

A state control circuit ( 107 ) gives an inactive state control signal (S 2 ) to a CPU ( 105 ) and an active state control signal (S 3 ) to a data transmission circuit ( 102 ). In response to this, the CPU ( 105 ) goes into the halt state and the data transmission circuit ( 102 ) goes into the receive state. When receive processing is completed, the state control circuit ( 107 ) gives an active state control signal (S 2 ) to the CPU ( 105 ). In response to this, the CPU ( 105 ) restores from the halt state to the operative state. The CPU ( 105 ) gives an instruction signal (CMD 2 ) to the state control circuit ( 107 ). The state control circuit ( 107 ) gives an inactive state control signal (S 3 ) to the data transmission circuit ( 102 ). In response to this, the data transmission circuit ( 102 ) goes into the halt state.

TECHNICAL FIELD

[0001] The present invention relates to an IC card, and moreparticularly, it relates to a contactless IC card that sends/receivesdata to/from the outside and is supplied with power from the outside ina contactless manner.

BACKGROUND ART

[0002] Recently, commercialization of an IC card system has beenactively proceeded in various industries in Japan. For example, in thetelephone industry, IC telephone cards have already been on sale andpublic telephones complying with IC cards have already been installed.Also, in the railway industry, an IC commutation ticket system isscheduled to be put in practical use in a few years. Furthermore,introduction of IC cards as substitution for identification cards suchas a license and a health insurance card is under examination.

[0003] IC cards are classified into contact cards and contactless cards.In a contact IC card, an external terminal is brought into contact witha reader/writer so as to send/receive data and be supplied with power.In contrast, in a contactless IC card, data are sent to and receivedfrom a reader/writer and power is supplied from a reader/writer in acontactless manner by using a self-contained antenna. Furthermore,contactless IC cards under development in various companies are tocomply with the anti-collision function of ISO 14443-3 for allowing onereader/writer to simultaneously write/read data in/from a plurality ofIC cards. Owing to this anti-collision function, an effect that, forexample, exchange of information on medical examination results andpayment for the examination can be simultaneously completed bysimultaneously subjecting a contactless IC card for hospital use and acontactless IC card for financial use to a reader/writer can beexpected.

[0004] In a contactless IC card, since power is supplied through radioconnection, the power supply is less stable than in a contact IC card.Therefore, in receiving a data from a reader/writer to store it in aself-contained nonvolatile memory or in reading a data from thenonvolatile memory to send it to a reader/writer, the data may not benormally received/sent due to the influence of noise caused by theoperation of the nonvolatile memory. Furthermore, also in the case whereone reader/writer simultaneously writes/reads data in/from a pluralityof IC cards, data transmission of one IC card may not be normallyconducted because of the influence of noise caused in anothercontactless IC card in storing a received data in the nonvolatile memoryor sending a data read from a nonvolatile memory to the reader/writer.

DISCLOSURE OF THE INVENTION

[0005] An object of the invention is providing an IC card capable ofsuppressing the influence of noise caused by the operation of anonvolatile memory.

[0006] According to the invention, the IC card of this invention is acontactless IC card that sends/receives data to/from the outside and issupplied with power from the outside in a contactless manner andincludes a transmission circuit, a buffer memory, a DMA circuit, anonvolatile memory, a CPU and state control means. The transmissioncircuit sends/receives data to/from the outside. The DMA circuittransmits a data received by the transmission circuit to the buffermemory and transmits a data stored in the buffer memory to thetransmission circuit. The CPU writes/reads data in/from the buffermemory and the nonvolatile memory. The state control circuit halts theoperations of the nonvolatile memory and the CPU while the transmissioncircuit is sending/receiving data to/from the outside.

[0007] In the IC card, the nonvolatile memory and the CPU halt theiroperations while the transmission circuit is sending/receiving datato/from the outside. Therefore, the influence on the transmissioncircuit of noise caused by the operations of the nonvolatile memory andthe CPU can be suppressed. As a result, the reliability in send/receiveprocessing by the transmission circuit can be improved. Furthermore,also in the case where one reader/writer reads/writes data in/from aplurality of IC cards, the nonvolatile memories and the CPUs of therespective IC cards halt their operations while the transmissioncircuits of the respective IC cards are sending/receiving data to/fromthe outside. Therefore, mutual interference by noise caused in therespective IC cards can be avoided, so as to improve the reliability inthe send/receive processing of the plural IC cards.

[0008] Preferably, a data bit appears every predetermined period in datasent/received by the transmission circuit. Also, the transmissioncircuit generates an interruption signal at timing between a period forsending/receiving one data bit and a period for sending/receivinganother data bit. The DMA circuit executes transmission processing inresponse to the interruption signal.

[0009] In the IC card, the DMA circuit executes the transmissionprocessing at timing between a period when one data bit is sent/receivedby the transmission circuit and a period when another data bit issent/received. Therefore, data sent/received by the transmission circuitcan be prevented from being changed due to the influence of noise causedby the operation of the DMA circuit.

[0010] Preferably, a data received by the transmission circuit has astructure in accordance with the standard of ISO/IEC 14443-3, and thetransmission circuit includes normal waveform storing means, possibleerror waveform storing means, waveform detecting means and collatingmeans.

[0011] The normal waveform storing means stores a waveform patternstandardized by ISO/IEC 14443-3. The possible error waveform storingmeans stores a waveform pattern including a possible error predictedwith respect to a data received by the transmission circuit. Thewaveform detecting means detects a waveform pattern of a data receivedby the transmission circuit. The collating means corrects the datareceived by the transmission circuit on the basis of the normal waveformpattern when the waveform pattern detected by the waveform detectingmeans accords with the waveform pattern stored in the normal waveformstoring means or the waveform pattern stored in the possible errorwaveform storing means.

[0012] In the IC card, when a data received by the transmission circuitincludes an error, the error can be corrected.

[0013] Preferably, a data received by the transmission circuit has astructure in accordance with the standard of ISO/IEC 14443-3, and thetransmission circuit includes an analog circuit part. The analog circuitpart modulates a data received from the outside into a digital data andoutputs the digital data. The IC card further includes preset signalgeneration means. The preset signal generation means gives the analogcircuit part a preset signal that is active during a period other than aperiod when the transmission circuit is receiving a data. The analogcircuit part sets an output thereof to a logical high level in responseto the active preset signal.

[0014] In the IC card, even though the signal output by the analogcircuit part falls to a logical low level in a period other than theperiod when the transmission circuit is receiving a data, thetransmission circuit can be prevented from going into the receive statewith the signal output by the analog circuit part at the logical lowlevel.

[0015] Preferably, a data received by the transmission circuit has astructure in accordance with the standard of ISO/IEC 14443-3, and thetransmission circuit includes an analog circuit part. The analog circuitpart modulates a data received from the outside into a digital data andoutputs the digital data. The IC card further includes hold signalgeneration means. The hold signal generation means gives the analogcircuit part a hold signal that is active during a period other than aperiod when the transmission circuit is receiving a data. The analogcircuit part sets, in response to the active hold signal, an outputthereof to a logical high level during a period other than the periodwhen the transmission circuit is receiving a data.

[0016] In the IC card, the hold signal generation means gives the analogcircuit part a hold signal that is active during a period other than aperiod when the transmission circuit is receiving a data. In response tothis active hold signal, the analog circuit part sets its output to alogical high level. Therefore, the transmission circuit can be preventedfrom going into the receive state with the signal output by the analogcircuit part at a logical low level.

[0017] Preferably, the IC card further includes a resume circuit. Whendata write processing on the nonvolatile memory executed by the CPU isinterrupted, the resume circuit stores a proceeding state of the writeprocessing up to time of interruption. The CPU resumes the writeprocessing on the nonvolatile memory on the basis of the proceedingstate stored in the resume circuit.

[0018] In the IC card, even when the write processing on the nonvolatilememory is interrupted, the write processing can be resumed from thestate attained at time of the interruption.

[0019] Preferably, the state control circuit includes a time countingcircuit. The time counting circuit starts counting time in response tothe CPU going into a halt state, stops counting the time in response torestoration of the CPU to an operative state and outputs a counted valueto the CPU.

[0020] When the CPU restores from the halt state to the operative state,it should be informed of time during which it was in the halt state. Ifan accessory timer of the CPU is used for informing the time duringwhich it was in the halt state, the CPU is operated at time intervalseven when the transmission circuit is sending/receiving data. Noise canbe caused by this operation of the CPU, and the noise can affect thedata transmission circuit.

[0021] In the IC card, the CPU can be completely placed in the haltstate while the transmission circuit is sending/receiving data owing tothe time counting circuit. Therefore, the CPU can be informed of thetime during which it was in the halt state without causing noise by theoperation of the CPU.

[0022] Preferably, the IC card further includes a time monitoringcircuit. The time monitoring circuit starts counting time in response tothe CPU going into a halt state and outputs a timeout signal to the CPUwhen the CPU does not restore to an operative state before a countedvalue reaches a given value. The CPU goes into the operative state inresponse to the timeout signal output by the time monitoring circuit.

[0023] In the IC card, the CPU can be prevented from being kept in thehalt state owing to the time monitoring circuit.

BRIEF DESCRIPTION OF DRAWINGS

[0024]FIG. 1 is a block diagram for showing the configuration of an ICcard according to Embodiment 1 of the invention.

[0025]FIG. 2 is a diagram for showing flow of processing in the IC cardof FIG. 1.

[0026]FIG. 3 is a diagram for showing transition of states of a CPU, anonvolatile memory, a state control circuit, a data RAM, a DMA circuitand a data transmission circuit shown in FIG. 1.

[0027]FIG. 4 is a block diagram for showing the configuration of a datatransmission circuit included in an IC card according to Embodiment 2 ofthe invention.

[0028]FIG. 5 is a diagram of a character format standardized by ISO/IEC14443-3.

[0029]FIG. 6 is a diagram for showing timing of a receive signal, a sendsignal and an interruption signal.

[0030]FIG. 7 is a diagram for showing states of a receive signal, a sendsignal, a data transmission circuit and a CPU.

[0031]FIG. 8 is a diagram for showing the structure of an SOFstandardized by ISO/IEC 14443-3.

[0032]FIG. 9 is a block diagram for showing the configuration of a datatransmission circuit included in an IC card according to Embodiment 3 ofthe invention.

[0033]FIG. 10 is a flowchart for showing the operation of the IC card ofEmbodiment 3 of the invention.

[0034]FIG. 11 is a block diagram for showing the configuration of a datatransmission circuit and a CPU included in an IC card according toEmbodiment 4 of the invention.

[0035]FIG. 12 is a diagram for showing the relationship between areceive signal and a preset signal.

[0036]FIG. 13 is a block diagram for showing the configuration of a datatransmission circuit and a CPU included in an IC card according toEmbodiment 5 of the invention.

[0037]FIG. 14 is a diagram for showing the relationship between areceive signal and a hold signal.

[0038]FIG. 15 is a block diagram for showing the configuration of aprincipal part of an IC card according to Embodiment 6 of the invention.

[0039]FIG. 16 is a diagram for explaining the operation of the IC cardshown in FIG. 15.

[0040]FIG. 17 is a flowchart for showing flow of write processing on anonvolatile memory in the IC card shown in FIG. 15.

[0041]FIG. 18 is a block diagram for showing the configuration of aprincipal part of an IC card according to Embodiment 7 of the invention.

[0042]FIG. 19 is a block diagram for showing the configuration of aprincipal part of an IC card according to Embodiment 8 of the invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0043] Preferred embodiments of the invention will now be described indetail with reference to the accompanying drawings. In the drawings,like reference numerals are used to refer to like or correspondingelements so as to avoid repeating the description.

[0044] (Embodiment 1)

[0045] <Configuration>

[0046]FIG. 1 is a block diagram for showing the configuration of an ICcard according to Embodiment 1 of the invention. Referring to FIG. 1,the IC card includes an antenna 101, a data transmission circuit 102, aDMA circuit 103, a data RAM 104, a CPU 105, a nonvolatile memory 106 anda state control circuit 107.

[0047] The antenna 101 receives a signal sent from a reader/writer (notshown) and sends a signal to the reader/writer. This sending/receivingis carried out in a contactless manner by using electric waves as amedium. Also, the antenna 101 receives power from the reader/writer byusing electromagnetic waves as a medium. This power serves as theoperation power of the IC card.

[0048] The data transmission circuit 102 processes a signal received bythe antenna 101 and transmits the processed signal to the DMA circuit103. Also, the data transmission circuit 102 processes a signaltransmitted from the DMA circuit 103 and transmits the processed signalto the antenna 101. Furthermore, the data transmission circuit 102 givesan interruption signal C1 to the state control circuit 110 inpredetermined cases.

[0049] The DMA circuit 103 writes a signal from the data transmissioncircuit 102 in the data RAM 104, and transmits a signal read from thedata RAM 104 to the data transmission circuit 102.

[0050] The CPU 105 writes/reads data in/from the data RAM 104 and thenonvolatile memory 106. Also, the CPU 105 gives an instruction signalCMD to the state control circuit 107.

[0051] The sate control circuit 107 gives a state control signal S1 tothe nonvolatile memory 106, a state control signal S2 to the CPU 105, astate control signal S3 to the data transmission circuit 102, a statecontrol signal S4 to the DMA circuit 103 and a state control signal S5to the data RAM 104.

[0052] The nonvolatile memory 106, the CPU 105, the data transmissioncircuit 102, the DMA circuit 103 and the data RAM 104 go into theoperative/halt state in response to the state control signals S1 throughS5, respectively.

[0053] <Operation>

[0054] Next, the operation of the IC card having the aforementionedconfiguration will be described with reference to FIG. 2. FIG. 2 is adiagram for showing flow of processing carried out in the IC card ofFIG. 1. Herein, the operation will be dividedly described with respectto (1) the case of data receive, (2) the case of data write/read in thenonvolatile memory and (3) the case of data transmission.

[0055] (1) Case of Data Receive:

[0056] It is first assumed that the CPU 105 is in the operative stateand that the data transmission circuit 102 is in the halt state. Underthese conditions, the CPU 105 gives an instruction signal CMD1 to thestate control circuit 107. The instruction signal CMD1 is an instructionto “place the data transmission circuit 102 in the receive state”.

[0057] When the instruction signal CMD1 is received, the state controlcircuit 107 gives an inactive state control signal S2 to the CPU 105. Inresponse to the inactive state control signal S2, the CPU 105 stops itsoperation. Also, the state control circuit 107 gives an active statecontrol signal S3 to the data transmission circuit 102. In response tothe active state control signal S3, the data transmission circuit 102goes into the receive state from the halt state.

[0058] The data transmission circuit 102 processes a signal received bythe antenna 101 so as to extract data d1 each having 8 bits. Also, thedata transmission circuit 102 gives an interruption signal C1 to thestate control circuit 107. The interruption signal C1 is a signalcorresponding to a request to “place the DMA circuit 103 in theoperative state”.

[0059] When the interruption signal C1 is received, the state controlcircuit 107 gives an active state control signal S4 to the DMA circuit103. In response to the active state control signal S4, the DMA circuit103 goes into the operative state from the halt state. Then, the DMAcircuit 103 controls to place the data RAM 104 in the operative state soas to write the data d1 each having 8 bits from the data transmissioncircuit 102 in the data RAM 104.

[0060] When the writing is completed, the DMA circuit 103 and the dataRAM 104 go into the halt state.

[0061] The processing from the extraction of the data d1 each having 8bits by the data transmission circuit 102 to the writing in the data RAM104 by the DMA circuit 103 is repeatedly executed on each data having 8bits.

[0062] When the processing of all the data is completed, namely, whenthe receive processing is completed, the data transmission circuit 102gives an interruption signal C2 to the state control circuit 107. Theinterruption signal C2 is a signal corresponding to a request to “placethe CPU 105 in the operative state”.

[0063] When the interruption signal C2 is received, the state controlcircuit 107 gives an active state control signal S2 to the CPU 105. Inresponse to the active state control signal S2, the CPU 105 restores tothe operative state from the halt state. The restored CPU 105 gives aninstruction signal CMD2 to the state control circuit 107. Theinstruction signal CMD2 is an instruction to “place the datatransmission circuit 102 in the halt state”.

[0064] When the instruction signal CMD2 is received, the state controlcircuit 107 gives an inactive state control signal S3 to the datatransmission circuit 102. In response to the inactive state controlsignal S3, the data transmission circuit 102 goes into the halt statefrom the receive state.

[0065] (2) Case of Data Write/Read in Nonvolatile Memory:

[0066] It is first assumed that the CPU 105 is in the operative stateand that the nonvolatile memory 106 is in the halt state. Under theseconditions, the CPU 105 gives an instruction signal CMD3 to the statecontrol circuit 107. The instruction signal CMD3 is an instruction to“place the nonvolatile memory 106 in the operative state”.

[0067] When the instruction signal CMD3 is received, the state controlcircuit 107 gives an active state control signal S1 to the nonvolatilememory 106. In response to the active state control signal S1, thenonvolatile memory 106 goes into the operative state from the haltstate. Then, the CPU 105 writes/reads data d2 in/from the nonvolatilememory 106.

[0068] When the writing/reading of the data d2 in/from the nonvolatilememory 106 is completed, the CPU 105 gives an instruction signal CMD4 tothe state control circuit 107. The instruction signal CMD4 is aninstruction to “place the nonvolatile memory 106 in the halt state”.

[0069] When the instruction signal CMD4 is received, the state controlcircuit 107 gives an inactive state control signal S1 to the nonvolatilememory 106. In response to the inactive state control signal S1, thenonvolatile memory 106 stops its operation.

[0070] (3) Case of Data Transmission:

[0071] It is first assumed that the CPU 105 is in the operative stateand that the data transmission circuit 102 is in the halt state. At thispoint, the CPU 105 stores data to be sent in the data RAM 104. Then, theCPU 105 gives an instruction signal CMD5 to the state control circuit107. The instruction signal CMD5 is an instruction to “place the datatransmission circuit 102 in the send state”.

[0072] When the instruction signal CMD5 is received, the state controlcircuit 107 gives an inactive state control signal S2 to the CPU 105. Inresponse to the inactive state control signal S2, the CPU 105 stops itsoperation. Also, the state control circuit 107 gives an active statecontrol signal S3 to the data transmission circuit 102. In response tothe active state control signal S3, the data transmission circuit 102goes into the send state from the halt state.

[0073] The data transmission circuit 102 gives an interruption signal C1to the state control circuit 107. The interruption signal C1 is a signalcorresponding to a request to “place the DMA circuit 103 in theoperative state”.

[0074] When the interruption signal C1 is received, the state controlcircuit 107 gives an active state control signal S4 to the DMA circuit103. In response to the active state control signal S4, the DMA circuit103 goes into the operative state from the halt state. Then, the DMAcircuit 103 controls to place the data RAM 104 in the operative state,so as to read data d3 each having 8 bits from the data RAM 104 totransfer them to the data transmission circuit 102. When the transfer iscompleted, the DMA circuit 103 and the data RAM 104 go into the haltstate.

[0075] The data transmission circuit 102 processes the data d3 eachhaving 8 bits from the DMA circuit 103 and sends the processed data tothe antenna 101.

[0076] The processing from the read by the DMA circuit 103 to thetransmission by the data transmission circuit 102 is repeatedly executedon each data having 8 bits.

[0077] When the processing of all the data to be sent is completed,namely, when the send processing is completed, the data transmissioncircuit 102 gives an interruption signal C2 to the state control circuit107. The interruption signal C2 is a signal corresponding to a requestto “place the CPU 105 in the operative state”.

[0078] In response to the interruption signal C2, the state controlcircuit 107 gives an active state control signal S2 to the CPU 105. Inresponse to the active state control signal S2, the CPU 105 restores tothe operative state from the halt state. The restored CPU 105 gives aninstruction signal CMD2 to the state control circuit 107. Theinstruction signal CMD2 is an instruction to “place the datatransmission circuit 102 in the halt state”.

[0079] When the instruction signal CMD2 is received, the state controlcircuit 107 gives an inactive state control signal S3 to the datatransmission circuit 102. In response to the inactive state controlsignal S3, the data transmission circuit 102 goes into the halt statefrom the send state.

[0080] <Transition of States>

[0081]FIG. 3 is a diagram for showing the transition of the states ofthe CPU 105, the nonvolatile memory 106, the state control circuit 107,the data RAM 104, the DMA circuit 103 and the data transmission circuit102 of FIG. 1. In FIG. 3, periods (1) through (3) respectivelycorrespond to periods (1) through (3) shown in FIG. 2. Also, “O” means“the operative state” and “H” means “the halt state”.

[0082] Referring to FIG. 3, during a period when the data transmissioncircuit 102 is in the receive state for processing a receive signal, theCPU 105 and the nonvolatile memory 106 are in the halt state.

[0083] Furthermore, also during a period when the data transmissioncircuit 102 is in the send state for outputting a send signal, the CPU105 and the nonvolatile memory 106 are in the halt state.

[0084] On the other hand, during a period when the CPU 105 is in theoperative state, the data transmission circuit 102 is in the halt state.

[0085] In this manner, the data transmission circuit 102 is operatedexclusively with the CPU 105 and the nonvolatile memory 106.

[0086] The DMA circuit 103 is in the operative state during a period fortransferring data while the data transmission circuit 102 is in thereceive state or in the send state. The data RAM 104 is in the operativestate during a period when the data transmission circuit 102 is in thereceive state or in the send state and the DMA circuit 103 is in theoperative state and during a period when the CPU 105 is in the operativestate. The state control circuit 107 is always in the operative state.

[0087] Each of a receive signal and a send signal is composed of an SOF(start of frame), a data portion and an EOF (end of frame) in accordancewith the standard of ISO/IEC 14443-3.

[0088] In this manner, in the IC card of Embodiment 1, the CPU 105 andthe nonvolatile memory 106 are in the halt state during a period whenthe data transmission circuit 102 is in the receive state for processinga receive signal and during a period when the data transmission circuit102 is in the send state for outputting a send signal. Therefore, theinfluence on the data transmission circuit 102 of noise caused by theoperations of the CPU 105 and the nonvolatile memory 106 can besuppressed. Accordingly, the reliability of the data transmissioncircuit 102 in the receive/send processing can be improved. Similarly,also in the case where one reader/writer simultaneously writes/readsdata in/from a plurality of IC cards, the nonvolatile memory and the CPUincluded in each of the IC cards stop their operations while thetransmission circuit of each IC card is sending/receiving data to/fromthe outside. Therefore, mutual interference due to noise caused in therespective IC cards can be prevented, so as to improve the reliabilityin receiving/sending data of the plural IC cards.

[0089] (Embodiment 2)

[0090] <Configuration>

[0091] An IC card according to Embodiment 2 of the invention includes adata transmission circuit 400 shown in FIG. 4 instead of the datatransmission circuit 102 of FIG. 1. Referring to FIG. 4, the datatransmission circuit 400 includes, in addition to the function of thedata transmission circuit 102 of FIG. 1, a send/receive processingcircuit 401 and a data transfer timing generation circuit 402.

[0092] The send/receive processing circuit 401 determines the state of areceive signal and a send signal from and to an analog circuit part (notshown) included in the data transmission circuit 400 in accordance withthe standard of ISO/IEC 14443-3, and outputs state information SMTcorresponding to the state.

[0093] The data transfer timing generation circuit 402 outputs aninterruption signal C3 to the state control circuit 107 in response tostate information SMT corresponding to “a signal currently received bythe data transmission circuit 400 being in a period of a stop bit”,state information SMT corresponding to “a signal currently sent by thedata transmission circuit 400 being in a period of H level (logical Hlevel) of the SOF”, or state information SMT corresponding to “a signalcurrently sent by the data transmission circuit 400 being in a period ofa stop bit”.

[0094] <Operation>

[0095] The operation of the IC card having the aforementionedconfiguration will now be described.

[0096] As described above, data to be sent or received is composed of anSOF, a data portion and an EOF in accordance with the standard ofISO/IEC 14443-3. The data portion complies with a character formatstandardized by ISO/IEC 14443-3 as shown in FIG. 5. A character includesa start bit at a first logical level, an 8-bit data at a second logicallevel and a stop bit and protection time at a third logical level.

[0097] Now, the operation will be dividedly described with respect to(a) the case of data receive and (b) the case of data transmission.

[0098] (a) Case of Data Receive:

[0099] This corresponds to (1) the case of data receive shown in FIG. 2.

[0100] First, when the data transmission circuit 102 is in the receivestate, a receive signal is input to the send/receive processing circuit401.

[0101] The send/receive processing circuit 401 determines the state ofthe receive signal in accordance with the standard of ISO/IEC 14443-3,and outputs state information SMT corresponding to the state.

[0102] When the state information SMT is received from the send/receiveprocessing circuit 401, a data transfer state control circuit 403determines whether or not the state information SMT corresponds to “asignal currently received by the data transmission circuit 400 being ina period of a stop bit”. As a result, when the state information SMT isdetermined to correspond to “a signal currently received by the datatransmission circuit 400 being in a period of a stop bit”, aninterruption signal C3 is output to the state control circuit 107. Thiscorresponds to the processing for giving the interruption signal C1 inFIG. 2.

[0103] In response to the interruption signal C3, the state controlcircuit 107 gives an active state control signal S4 to the DMA circuit103. This corresponds to the case of giving the active state signal S4in FIG. 2.

[0104] In response to the active state control signal S4, the DMAcircuit 103 goes into the operative state from the halt state. Then, theDMA circuit 103 controls to place the data RAM 104 in the operativestate so as to write data d1 each having 8 bits from the datatransmission circuit 102 in the data RAM 104. When the transfer iscompleted, the DMA circuit 103 and the data RAM 104 go into the haltstate.

[0105] (b) Case of Data Transmission:

[0106] This corresponds to (3) the case of transmission shown in FIG. 2.

[0107] The send/receive processing circuit 401 receives a signal sent bythe data transmission circuit 102. Then, the send/receive processingcircuit 401 determines the state of the receive signal in accordancewith the standard of ISO/IEC 14443-3, and outputs state information SMTcorresponding to the state.

[0108] When the state information SMT is received from the send/receiveprocessing circuit 401, the data transfer state control circuit 403determines whether or not the state information SMT corresponds to “asignal currently sent by the data transmission circuit 400 being in aperiod of H level (logical H level) of the SOF” or “a signal currentlysent by the data transmission circuit 400 being in a period of a stopbit”. As a result, when the state information SMT is determined to beeither, an interruption signal C3 is output to the state control circuit107. This corresponds to the processing for giving the interruptionsignal C1 in FIG. 2.

[0109] In response to the interruption signal C3, the state controlcircuit 107 gives an active state control signal S4 to the DMA circuit103. This corresponds to the case of giving the active state signal S4in FIG. 2.

[0110] In response to the active state control signal S4, the DMAcircuit 103 goes into the operative state from the halt state. Then, theDMA circuit 103 controls to place the data RAM 104 in the operativestate so as to read data d3 each having 8 bits from the data RAM 104 totransfer them to the data transmission circuit 102. When the transfer iscompleted, the DMA circuit 103 and the data RAM 104 go into the haltstate.

[0111]FIG. 6 is a diagram for showing timing of a receive signal, a sendsignal and an interruption signal C3. As shown in FIG. 6, the datatransfer timing generation circuit 402 outputs an interruption signal C3in a period between one 8-bit data period and another 8-bit data periodin the receive signal or the send signal.

[0112] In this manner, according to Embodiment 2, since the send/receiveprocessing circuit 401 and the data transfer timing generation circuit402 are provided, data can be transferred by the DMA circuit 102 attiming between a period corresponding to one 8-bit data and a periodcorresponding to another 8-bit data in a signal received or sent by thedata transmission circuit 102. As a result, the signal received/sent bythe data transmission circuit 102 can be prevented from being changeddue to the influence of noise caused by the operation of the DMA circuit102.

[0113] (Embodiment 3)

[0114] In the data transmission circuit 102 of FIG. 1, a signal receivedby the antenna 101 is modulated into digital data by an analog circuitpart (not shown) such as a modulator, so as to obtain a receive signalas shown in FIG. 7. As shown in FIG. 7, a receive signal is composed ofan SOF, a data portion and an EOF and is at a logical high level whenthe data transmission circuit 102 is in a state other than the receivestate. Also, the SOF has a structure according with the standard ofISO/IEC 14443-3 as shown in FIG. 5. The SOF is composed of a fall at afirst logical level, 10-etu period low (logical low level) at a secondlogical level, a rise within 1 etu at a third logical level and 2through 3-etu period high (logical high level) at a fourth logicallevel. It is noted that etu is a unit of time.

[0115] However, when the data transmission circuit 102 is in a stateother than the receive state, the analog circuit part can be affected bynoise caused by the operations of the CPU 105, the nonvolatile memory106 and the like, so that a receive signal may fall to a logical lowlevel when the data transmission circuit 102 is in a state other thanthe receive state. As a result, there arises a problem that the SOFcannot be correctly identified in a logic circuit part following theanalog circuit part. The object of an IC card according to Embodiment 3is overcoming this problem.

[0116] <Configuration>

[0117] The IC card of Embodiment 3 of this invention includes a datatransmission circuit 700 of FIG. 9 instead of the data transmissioncircuit 102 of FIG. 1. Referring to FIG. 9, the data transmissioncircuit 700 has the function of the data transmission circuit 102 ofFIG. 1 and additionally includes a normal waveform storing circuit 701,a possible error waveform storing circuit 702, a receive waveformdetecting circuit 703 and a waveform pattern collating circuit 704.

[0118] The normal waveform storing circuit 701 stores a waveform patternof the SOF according to the standard of ISO/IEC 14443-3. The possibleerror waveform storing circuit 702 stores a previously predicted errorwaveform pattern. For example, in the case where the analog circuit partis affected by noise caused by the operations of the CPU 105, thenonvolatile memory 106 and the like when the data transmission circuit102 is in a state other than the receive state, the SOF of a receivesignal has a waveform pattern having a fall earlier than the fall at afirst logical level according to the standard of ISO/IEC 14443-3. Such apreviously predicted error waveform pattern is stored. The receivewaveform detecting circuit 703 detects the waveform pattern of the SOFof a receive signal output from the analog circuit part. The waveformpattern collating circuit 704 determines whether or not the waveformpattern of the SOF detected by the receive waveform detecting circuit703 accords with the waveform pattern stored in the normal waveformstoring circuit 701 or the waveform pattern stored in the possible errorwaveform storing circuit 702. When it accords with either waveformpattern, the waveform pattern of the SOF of the receive signal iscorrected to the waveform pattern stored in the normal waveform storingcircuit 701.

[0119] <Operation>

[0120] Now, the operation of the IC card having the aforementionedconfiguration will be described with reference to FIG. 10.

[0121] Previously, a waveform pattern according to the standard ofISO/IEC 14443-3 is stored in the normal waveform storing circuit 701 anda predicted error waveform pattern is stored in the possible errorwaveform storing circuit 702.

[0122] In step ST1001, a waveform pattern of the SOF of a receive signaloutput from the analog circuit part is detected by the receive waveformdetecting circuit 703.

[0123] Subsequently, in step ST1002, the waveform pattern of the SOF ofthe receive signal is collated with the waveform pattern stored in thenormal waveform storing circuit 701 and the waveform pattern stored inthe possible error waveform storing circuit 702.

[0124] Next, in step ST1003, it is determined whether or not thewaveform pattern of the SOF of the receive signal accords with thewaveform pattern stored in the normal waveform storing circuit 701 orthe waveform pattern stored in the possible error waveform storingcircuit 702.

[0125] When it is determined that the waveform pattern accords witheither, the procedure proceeds to step ST1004. Then, in step ST1004, thewaveform pattern of the SOF of the receive signal is corrected to thewaveform pattern stored in the normal waveform storing circuit 701.

[0126] When it is determined that the waveform pattern accords withneither, the procedure returns to step ST1001.

[0127] In this manner, according to Embodiment 3, when a receive signalincludes a previously predicted error, it can be corrected. Accordingly,the problem that the SOF cannot be correctly identified in the logiccircuit part following the analog circuit part can be avoided.

[0128] Although the number of possible error waveform storing circuit702 is herein one, it can be plural in number. Thus, a larger number ofpattern errors possibly included in a receive signal can be corrected.

[0129] (Embodiment 4)

[0130] <Configuration>

[0131] An IC card according to Embodiment 4 of the invention includes adata transmission circuit 1100 and a CPU 1110 of FIG. 11 instead of thedata transmission circuit 102 and the CPU 105 of FIG. 1.

[0132] Referring to FIG. 11, the data transmission circuit 1100 includesa sending/receiving circuit 1101 and a demodulating circuit 1102. Thesending/receiving circuit 1101 transmits a signal received by theantenna 101 to the demodulating circuit 1102. The demodulating circuit1102 demodulates the signal from the sending/receiving circuit 1101 intoa digital signal to be output. The signal output from the demodulatingcircuit 1102 is similar to the receive signal shown in FIG. 7. Thesignal output from the demodulating circuit 1102 is processed by afollowing logical circuit part (not shown) to be transmitted by the DMAcircuit 103. Also, the demodulating circuit 102 sets the level of itsoutput signal to a logical high level in response to an active presetsignal PR.

[0133] The CPU 1110 includes preset signal generation means 1111. Thepreset signal generation means 1111 gives the demodulating circuit 1102a preset signal PR that is active for a predetermined period while thedata transmission circuit 1100 is in a state other than the receivestate.

[0134] <Operation>

[0135] As shown in FIG. 7, the signal output from the demodulatingcircuit 1102 is at a logical high level when the data transmissioncircuit 102 is in a state other than the receive state. However, in thecase where the demodulating circuit 1102 malfunctions due to noisecaused by the operations of the CPU 105 and the nonvolatile memory 106or by conducting the send processing when the data transmission circuit102 is in a state other than the receive state, the signal output fromthe demodulating circuit 1102 may fall to a logical low level as shownin FIG. 12. If the data transmission circuit 1100 goes into the receivestate with the signal output from the demodulating circuit 1102 at alogical low level, a fall of the SOF cannot be correctly identified inthe following logical circuit part.

[0136] In the IC card of Embodiment 4, as shown in FIG. 12, the presetsignal generation means 1111 gives the demodulating circuit 1102 apreset signal PR that is active during a predetermined period while thedata transmission circuit 1100 is in a state other than the receivestate. In response to the active preset signal PR, the demodulatingcircuit 1102 sets the level of its output signal to a logical highlevel. Therefore, even when the signal output from the demodulatingcircuit 1102 falls to a logical low level, the data transmission circuitcan be prevented from going into the receive state with the signaloutput from the demodulating circuit 1102 at a logical low level. As aresult, a fall of the SOF can be correctly identified in the followinglogic circuit part.

[0137] (Embodiment 5)

[0138] <Configuration>

[0139] An IC card according to Embodiment 5 of the invention ischaracterized by including hold signal generation means 1301 of FIG. 13instead of the preset signal generation means 1111 of FIG. 11.

[0140] Referring to FIG. 13, the hold signal generation means 1301 givesthe demodulating circuit 1102 a hold signal HL that is active during aperiod while the data transmission circuit 1100 is in a state other thanthe receive state. In response to the active hold signal HL, thedemodulating circuit 1102 sets the level of its output signal to alogical high level.

[0141] <Operation>

[0142] In the IC card having the aforementioned configuration, as shownin FIG. 14, the hold signal generation means 1301 gives the demodulatingcircuit 1102 a hold signal HL that is active during a period while thedata transmission circuit 1100 is in a state other than the receivestate. In response to the active hold signal HL, the demodulatingcircuit 1102 sets the level of its output signal to a logical highlevel. Thus, the data transmission circuit can be prevented from goinginto the receive state with the signal output from the demodulatingcircuit 1102 at a logical low level. As a result, a fall of the SOF canbe correctly identified in the following logic circuit part.

[0143] (Embodiment 6)

[0144]FIG. 15 is a block diagram for showing the configuration of aprincipal part of an IC card according to Embodiment 6 of the invention.Referring to FIG. 15, the IC card is characterized by including a resumecircuit 1501 within the state control circuit 107. The rest of theconfiguration is the same as that of the IC card shown in FIG. 1.

[0145] When the nonvolatile memory 106 goes into the halt state from theoperative state, the resume circuit 1501 stores time spent on the writeprocessing on the nonvolatile memory 106, and an address and data forthe write processing.

[0146] Next, the operation of the IC card having the aforementionedconfiguration will be described with reference to FIG. 16.

[0147] In the case where a data is to be written in the nonvolatilememory 106, the CPU 105 gives an instruction signal CMD3 to the statecontrol circuit 107 first. The instruction signal CMD3 is an instructionto “place the nonvolatile memory 106 in the operative state”.

[0148] When the instruction signal CMD3 is received, the state controlcircuit 107 gives an active state control signal S1 to the nonvolatilememory 106. In response to the active state control signal S1, thenonvolatile memory 106 goes into the operative state from the haltstate.

[0149] On the other hand, the resume circuit 1501 starts counting timein response to the instruction signal CMD3.

[0150] In order to completely write a data in the nonvolatile memory106, a voltage should be applied for a predetermined time period.Herein, it is assumed that a voltage should be applied for a period of10 ms. After starting the write processing in the nonvolatile memory106, the CPU 105 refers the time shown by the resume circuit 1501. Whenthe time reaches 10 ms, it is determined that the data has beencompletely written. Then, the CPU 105 gives an instruction signal CMD4to the state control circuit 107. The instruction signal CMD4 is aninstruction to “place the nonvolatile memory 106 in the halt state”.

[0151] When the instruction signal CMD4 is received, the state controlcircuit 107 gives an inactive state control signal S1 to the nonvolatilememory 106. In response to the inactive state control signal S1, thenonvolatile memory 106 stops its operation.

[0152] At this point, processing to be conducted when a send processinginstruction is issued by the CPU 105 after the write processing on thenonvolatile memory 106 is started and before the time shown by theresume circuit 1501 reaches 10 ms will be described.

[0153] It is herein assumed that the CPU 105 gives an instruction signalCMD5 to the state control circuit 107 before the time shown by theresume circuit 1501 reaches 10 ms, namely, when the time is, forexample, 7 ms. The instruction signal CMD5 is an instruction to “placethe data transmission circuit 102 in the send state”.

[0154] In response to the instruction signal CMD5, the resume circuit107 stores a state of the write processing attained at this point,namely, an address and data for the write processing and time spent onthe write processing up to this point (herein 7 ms).

[0155] On the other hand, when the instruction signal CMD5 is received,the state control circuit 107 gives an inactive state control signal S2to the CPU 105. In response to the inactive state control signal S2, theCPU 105 stops its operation. Also, the state control circuit 107 givesan active state control signal S3 to the data transmission circuit 102.In response to the active state control signal S3, the data transmissioncircuit 102 goes into the send state from the halt state. Thereafter,the send processing is carried out in the same manner as shown in FIG.2.

[0156] When the send processing is completed, the data transmissioncircuit 102 gives an interruption signal C2 to the state control circuit107. The interruption signal C2 is a signal corresponding to a requestto “place the CPU 105 in the operative state”.

[0157] In response to the interruption signal C2, the state controlcircuit 107 gives an active state control signal S2 to the CPU 105. Inresponse to the active state control signal S2, the CPU 105 restores tothe operative state from the halt state.

[0158] The restored CPU 105 gives an instruction signal CMD2 to thestate control circuit 107. The instruction signal CMD2 is an instructionto “place the data transmission circuit 102 in the halt state”. When theinstruction signal CMD2 is received, the state control circuit 107 givesan inactive state control signal S3 to the data transmission circuit102. In response to the inactive state control signal S3, the datatransmission circuit 102 goes into the halt state from the send state.

[0159] Furthermore, the restored CPU 105 gives an instruction signalCMD3 to the state control circuit 107. The instruction signal CMD3 is aninstruction to “place the nonvolatile memory 106 in the operativestate”. When the instruction signal CMD3 is received, the state controlcircuit 107 gives an active state control signal S1. In response to theactive state control signal S1, the nonvolatile memory 106 goes into theoperative state. The CPU 105 resumes the write processing from the state(the address, the data and the time spent on the processing) stored inthe resume circuit 1501. The resume circuit 1501 counts timecontinuously from the stored time (herein 7 ms).

[0160] When the time reaches 10 ms, the CPU 105 gives an instructionsignal CMD4 to the state control circuit 107. The instruction signalCMD4 is an instruction to “place the nonvolatile memory 106 in the haltstate”. When the instruction signal CMD4 is received, the state controlcircuit 107 gives an inactive state control signal S1 to the nonvolatilememory 106. In response to the inactive state control signal S1, thenonvolatile memory 106 stops its operation.

[0161] Also in the case where the CPU 105 issues a receive processinginstruction after the write processing is started in the nonvolatilememory 106 and before the time shown by the resume circuit 1501 reaches10 ms, the processing is carried out in the same manner as describedabove.

[0162] <Flowchart>

[0163]FIG. 17 is a flowchart for showing the flow of the writeprocessing on the nonvolatile memory of the IC card of FIG. 15. The flowof the processing will now be described with reference to FIG. 17.

[0164] First, in step ST1701, it is determined whether or not the writeprocessing is to be executed on the nonvolatile memory 106. In the casewhere the write processing is to be executed, the procedure proceeds tostep ST1701.

[0165] Next, in step ST1702, it is determined whether or not previouswrite processing is completely ended. This is determined by referringthe time stored in the resume circuit 1501. When the time stored in theresume circuit 1501 does not reach time required for completing thewrite processing, it is determined that the previous write processing isinterrupted, and the procedure proceeds to step ST1703.

[0166] In step ST1703, the CPU 105 resumes the write processing from thestate (the address, the data and the time spent on the processing)stored in the resume circuit 1501. The resume circuit 1501 counts timecontinuously from the stored time.

[0167] On the other hand, when the time stored in the resume circuit1501 has reached the time required for completing the write processingin step ST1702, it is determined that the previous write processing hasbeen completely ended, and the procedure proceeds to step ST1704.

[0168] In step ST1704, the CPU 105 starts the write operation from thebeginning. The resume circuit 1501 starts counting time from thebeginning.

[0169] Next, in step ST1705, in the case where the send/receiveprocessing is started before the time counted by the resume circuit 1501reaches the time required for completing the write processing, theprocedure proceeds to step ST1706.

[0170] In step ST1706, the resume circuit 107 stores a state of thewrite operation attained at this point, namely, an address and data forthe write processing and time spent on the write processing up to thispoint. Then, the procedure returns to step ST1701.

[0171] On the other hand, when the send/receive processing is notstarted in step ST1705, the procedure proceeds to step ST1707. In stepST1707, it is determined whether or not the time counted by the resumecircuit 1501 reaches the time required for completing the writeprocessing, and when it reaches, the procedure proceeds to step ST1708,where the write processing is ended.

[0172] In this manner, since the IC card of Embodiment 6 of theinvention includes the resume circuit 1501, even when the writeprocessing on the nonvolatile memory 106 is interrupted by asend/receive processing instruction, the write processing can be resumedfrom the state attained when it was interrupted.

[0173] (Embodiment 7)

[0174]FIG. 18 is a block diagram for showing the configuration of aprincipal part of an IC card according to Embodiment 7 of the invention.Referring to FIG. 18, the IC card is characterized by including a timecounting circuit 1801 within the state control circuit 107. The rest ofthe configuration is the same as that of the IC card of FIG. 1.

[0175] The time counting circuit 1801 starts counting time in responseto instruction signals CMD1 and CMD5 output from the CPU 105. Theinstruction signal CMD1 is an instruction to “place the datatransmission circuit 102 in the receive state”. The instruction signalCMD5 is an instruction to “place the data transmission circuit 102 inthe send state”. The time count is stopped in response to aninterruption signal C2 from the data transmission circuit 102, and acounted value is output to the CPU 105.

[0176] Next, the operation of the IC card having the aforementionedconfiguration will be described.

[0177] When the CPU 105 gives an instruction signal CMD1 or CMD5 to thestate control circuit 107, the time counting circuit 1801 startscounting time. In response to the instruction signal CMD1 or CMD5, theIC card carries out the receive processing or the send processing.

[0178] When the receive processing or the send processing is completed,the data transmission circuit 102 gives an interruption signal C2 to thestate control circuit 107. The interruption signal C2 is a signalcorresponding to a request to “place the CPU 105 in the operativestate”.

[0179] In response to the interruption signal C2, the time countingcircuit 1801 stops counting time and outputs a counted value to the CPU105.

[0180] As shown in FIG. 7, the CPU 105 is in the halt state when thedata transmission circuit 102 is in the receive or send state. When theCPU 105 restores from the halt state to the operative state, however, itshould be informed of time during which it was in the halt state (thatis, system time spent on receive processing or system time spent on sendprocessing shown in FIG. 7). In the case where an accessory timer of theCPU 105 is used for being informed of the time during which it was inthe halt state, the CPU 105 is operated at predetermined time intervalswhile the data transmission circuit 102 is in the receive state or inthe send state. Noise is caused by this operation of the CPU 105, andthe noise can affect the data transmission circuit 102 in the receivestate or in the send state.

[0181] Since the IC card of FIG. 18 includes the time counting circuit1801, the CPU 105 can be completely placed in the halt state while thedata transmission circuit 102 is in the receive state or in the sendstate. Accordingly, the CPU 105 can be informed of the time during whichit was in the halt state without causing noise by the operation of theCPU 105.

[0182] (Embodiment 8)

[0183]FIG. 19 is a block diagram for showing the configuration of aprincipal part of an IC card according to Embodiment 8 of the invention.Referring to FIG. 19, the IC card is characterized by including a timemonitoring circuit 1901 within the state control circuit 107. The restof the configuration is the same as that of the IC card of FIG. 1.

[0184] The time monitoring circuit 1901 starts counting time in responseto an instruction signal CMD1 from the CPU 105. The instruction signalCMD1 is an instruction to “place the data transmission circuit 102 inthe receive state”. The time monitoring circuit 1901 stops counting timein response to an interruption signal C2 from the data transmissioncircuit 102 and resets a counted value. On the other hand, when thecounted time value reaches a predetermined value, namely, when aninterruption signal C2 is not given to the state control circuit 107until the counted value reaches a predetermined value, the timemonitoring circuit 1901 outputs a timeout signal TO to the CPU 105.

[0185] Next, the operation of the IC card having the aforementionedconfiguration will be described.

[0186] When the CPU 105 gives an instruction signal CMD1 to the statecontrol circuit 107, the time monitoring circuit 1901 starts countingtime. In response to the instruction signal CMD1, the data transmissioncircuit 102 goes into the receive state.

[0187] When the receive processing is completed, the data transmissioncircuit 102 gives an interruption signal C2 to the state control circuit107. The interruption signal C2 is a signal corresponding to a requestto “place the CPU 105 in the operative state”.

[0188] In response to the interruption signal C2, the time monitoringcircuit 1901 stops counting time and resets the counted value.

[0189] When an interruption signal C2 is not given to the state controlcircuit 107 until the counted time value of the time monitoring circuit1901 reaches a predetermined value, the time monitoring circuit 1901outputs a timeout signal TO to the CPU 105.

[0190] In response to the timeout signal TO, the CPU 105 restores to theoperative state and carries out timeout processing.

[0191] In this manner, since the IC card of Embodiment 9includes thetime monitoring circuit 1901, the CPU 105 can restore from the haltstate to the operative state when an interruption signal C2 is not givento the state control circuit 107 until a counted value reaches apredetermined value. Accordingly, the CPU 105 can be prevented frombeing kept in the halt state, for example, when a receive data cannot bereceived for a long period of time after the data transmission circuit102 going into the receive state.

1. A contactless IC card that sends/receives data to/from the outsideand is supplied with power from the outside in a contactless manner,comprising: a transmission circuit for sending/receiving data to/fromthe outside; a buffer memory; a DMA circuit for transmitting datareceived by said transmission circuit to said buffer memory andtransmitting data stored in said buffer memory to said transmissioncircuit; a nonvolatile memory; a CPU for executing write/read processingon said buffer memory and said nonvolatile memory; and state controlmeans for halting operations of said nonvolatile memory and said CPUwhile said transmission circuit is sending/receiving data to/from theoutside.
 2. The IC card of claim 1, wherein a data bit appears everypredetermined period in data sent/received by said transmission circuit,said transmission circuit generates an interruption signal at timingbetween a period for sending/receiving one data bit and a period forsending/receiving another data bit, and said DMA circuit executestransmission processing in response to the interruption signal.
 3. TheIC card of claim 1, wherein a data received by said transmission circuithas a structure in accordance with the standard of ISO/IEC 14443-3, andsaid transmission circuit includes: normal waveform storing means forstoring a waveform pattern standardized by ISO/IEC 14443-3; possibleerror waveform storing means for storing a waveform pattern including apossible error predicted with respect to a data received by saidtransmission circuit; waveform detecting means for detecting a waveformpattern of a data received by said transmission circuit; and collatingmeans for correcting the data received by said transmission circuit onthe basis of said normal waveform pattern when said waveform patterndetected by said waveform detecting means accords with said waveformpattern stored in said normal waveform storing means or said waveformpattern stored in said possible error waveform storing means.
 4. The ICcard of claim 1, wherein a data received by said transmission circuithas a structure in accordance with the standard of ISO/IEC 14443-3, saidtransmission circuit includes an analog circuit part for modulating adata received from the outside into a digital data and outputting saiddigital data, said IC card further comprises preset signal generationmeans for giving said analog circuit part a preset signal that is activeduring a period other than a period when said transmission circuit isreceiving a data, and said analog circuit part sets an output thereof toa logical high level in response to the active preset signal.
 5. The ICcard of claim 5, wherein a data received by said transmission circuithas a structure in accordance with the standard of ISO/IEC 14443-3, saidtransmission circuit includes an analog circuit part for modulating adata received from the outside into a digital data and outputting saiddigital data, said IC card further comprises hold signal generationmeans for giving said analog circuit part a hold signal that is activeduring a period other than a period when said transmission circuit isreceiving a data, and said analog circuit part sets, in response to theactive hold signal, an output thereof to a logical high level during aperiod other than the period when said transmission circuit is receivinga data.
 6. The IC card of claim 1, further comprising a resume circuitfor storing, when data write processing on said nonvolatile memoryexecuted by said CPU is interrupted, a proceeding state of the writeprocessing up to time of interruption, wherein said CPU resumes thewrite processing on said nonvolatile memory on the basis of saidproceeding state stored in said resume circuit.
 7. The IC card of claim1, wherein said state control circuit includes a time counting circuitfor starting counting time in response to said CPU going into a haltstate, stopping counting the time in response to restoration of said CPUto an operative state and outputting a counted value to said CPU.
 8. TheIC card of claim 1, further comprising a time monitoring circuit forstarting counting time in response to said CPU going into a halt stateand outputting a timeout signal to said CPU when said CPU does notrestore to an operative state before a counted value reaches a givenvalue, wherein said CPU goes into the operative state in response to thetimeout signal output by said time monitoring circuit.